1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device, which includes a forming method of a dual damascene structure using a so-called dual hard mask.
2. Description of the Related Art
In the wiring structure of the dual damascene structure, a silicon oxide layer is used as a connection layer in which a connection hole is formed, an organic film is used as a wiring layer in which groove wiring lines are formed, a silicon oxide film is used as a lower layer hard mask, and a silicon nitride film is used as an upper layer hard mask.
Hereinafter, a method of manufacturing groove wiring lines using a conventional dual hard mask method will be described with reference to manufacturing process sectional views of FIGS. 3A to 3G.
Although not shown, for example, after a semiconductor element, a wiring line and the like are formed on a semiconductor substrate by a well-known semiconductor process technique, an interlayer insulating film covering the semiconductor element, the wiring line and the like is formed. Next, for example, a silicon nitride film for preventing diffusion of copper is formed on the interlayer insulating film, and further, an insulating film in which a groove wiring line is formed, is formed of, for example, a silicon oxide film.
Next, by using a normal forming technique of a groove wiring line, a groove for formation of a wiring line is formed in the silicon oxide film. Then, a barrier layer for preventing diffusion of copper is formed on the inner surface of the groove, and further, after copper is embedded in the inside of the groove through the barrier layer, the surplus copper and barrier layer on the silicon oxide film are removed, and a first wiring line is formed in the inside of the groove. In this way, a base body 110 as shown in FIG. 3A is formed.
Thereafter, for example, by a PE-CVD (Plasma Enhancement) (Chemical Vapor Deposition) method, a barrier layer 111 made of a silicon nitride film for preventing diffusion of copper is formed to a thickness of, for example, 50 nm on the base body 110. Next, for example, by the PE-CVD method, a first insulating film 112, which becomes a connection layer in which a connection hole is formed, is formed on the barrier layer 111 by forming, for example, a silicon oxide film of a thickness of 500 nm.
Next, for example, by the PE-CVD method, an organic film of a thickness of, for example, 400 nm is formed on the first insulating film 112 so that a second insulating film 113 is formed.
Next, by a chemical vapor deposition (hereinafter referred to as CVD) method or a physical vapor deposition (hereinafter referred to as PVD) method, a lower layer hard mask 114 is formed on the second insulating film 113 by forming, for example, a silicon oxide film of a thickness of 200 nm. Further, an upper layer hard mask 115 of, for example, a silicon nitride film of a thickness of 100 nm is formed on the lower layer hard mask 114.
Next, although not shown, after a resist mask (not shown) which becomes an etching mask for formation of a groove is formed by resist coating and a lithography technique, the upper layer hard mask 115 is subjected to, for example, anisotropic etching by an etching technique using the resist mask, so that an opening 116 for formation of a wiring groove is formed. Thereafter, the resist mask is removed by a normal resist removal technique Next, as shown in FIG. 3B, a resist mask 117 is formed on the hard mask 115 including the inside of the opening 116 by the resist coating technique. Then, an opening 118 for formation of a connection hole is formed in the resist film 117 by the lithography technique.
As an example of the etching conditions of the upper layer hard mask 115 made of the silicon nitride film, for example, a magnetron etching apparatus was used, trifluoromethane (CHF3) (supply flow rate was, for example, 20 cm3/min), argon (Ar) (supply flow rate was, for example, 200 cm3/min) and oxygen (O2) (supply flow rate was, for example, 10 cm3/min) were used as etching gases, the pressure of an etching atmosphere was set to 10 Pa, and the substrate temperature was set to 0xc2x0 C.
Next, as shown in FIG. 3C, the resist film 117 is used as a mask, and the lower hard mask 114 is subjected to, for example, anisotropic etching by an etching technique to form a connection hole pattern 119.
As an example of the etching conditions of the lower layer hard mask 114 made of the silicon oxide film, for example, a magnetron etching apparatus was used, octafluorocyclobutane (C4F8) (supply flow rate was, for example, 20 cm3/min), argon (Ar) (supply flow rate was, for example, 200 cm3/min) and oxygen (O2) (supply flow rate was, for example, 10 cm3/min) were used as etching gases, the pressure of an etching atmosphere was set to 10 Pa, and the substrate temperature was set to 0xc2x0 C.
Further, as shown in FIG. 3D, the etching is made to proceed while the lower layer hard mask 114 is used as a mask, and the connection hole pattern 119 is formed to extend into the second insulating film 113 made of the organic film. In this etching, since the organic film is etched while the lower mask 114 made of the silicon oxide film is used as the etching mask, the first insulating film 112 made of the silicon oxide film functions as an etching stopper. Besides, in this etching, since the resist mask 117 (see FIG. 3C) is also etched and is removed, an etching process for removing only the resist mask 117 is not required.
As an example of the etching conditions of the organic film, for example, an electron cyclotron resonance (hereinafter referred to as ECR) etching apparatus was used, ammonia (NH3) (supply flow rate was, for example, 100 cm3/min) was used as an etching gas, and the pressure of an etching atmosphere was set to 3 Pa.
Next, as shown in FIG. 3E, the wiring groove pattern 116 is formed to extend into the lower hard mask 114 while the upper layer hard mask 115 is used as the etching mask, and a connection hole 121 is formed in the first insulating film 112 while the second insulating film 113 is used as an etching mask. In this etching, over etching for etching the silicon oxide film of a thickness of 500 nm is applied to the upper layer hard mask 115. Thus, the wiring groove pattern 116 moves back.
Next, as shown in FIG. 3F, the upper layer hard mask 115 and the lower layer hard mask 114 are used as etching masks, and a wiring groove 122 is formed in the second insulating film 113.
Further, as shown in FIG. 3G, the first insulating film 112 is used as an etching mask, and the barrier layer 111 made of the silicon nitride film exposed at the bottom of the connection hole 121 is removed by etching. At this time, the upper layer hard mask 115 (see FIG. 3F) is also removed at the same time. As an example of the etching conditions of the silicon nitride film, for example, a magnetron etching apparatus was used, trifluoromethane (CHF3) (supply flow rate was, for example, 20 cm3/min), argon (Ar) (supply flow rate was, for example, 200 cm3/min) and oxygen (O2) (supply flow rate was, for example, 10 cm3/min) were used as etching gases, the pressure of an etching atmosphere was set to 10 Pa, and the substrate temperature was set to 0xc2x0 C.
In this way, the wiring groove 122 is formed in the second insulating film 113, and the connection hole 121 communicating with the first wiring line (not shown) is formed in the first insulating film 112.
However, in the conventional technique, since etching selectivity to the upper layer hard mask is insufficient, when the wiring groove pattern is formed in the lower layer hard mask while the upper layer hard mask is used as the etching mask, there arises a problem that the wiring groove pattern is formed to be enlarged when the wiring groove pattern formed in the mask is enlarged, the wiring groove formed in the second insulating film is formed to be larger than a design size, so that short circuit failure occurs when a conductive material is embedded in the wiring groove to form a wiring line.
In order to prevent the enlargement of the wiring groove, it is effective to thicken the upper layer hard mask. However, when the upper layer hard mask is thickened, there arises a problem at the photolithography step for forming the connection hole pattern in the lower layer hard mask. In general, in the photolithography step including a stepped portion, an anti-reflection film of a thickness of about 50 nm to 100 nm is formed as an under layer of a photosensitive resist. By forming the anti-reflection film, light beams irradiated at the time of exposure are prevented from being reflected by the under layer, and the resolution is improved. However if there is a stepped portion at the time of formation of the anti-reflection film, since the film formation of the anti-reflection film can not be uniformly carried out, there arises a problem that the resolution at the photolithography step is lowered. Especially, in the case where the under layer stepped portion exceeds 100 nm, it becomes difficult to form the anti-reflection film in an excellent state.
For example, the minimum resolution diameter at the photolithography step of forming an opening for formation of a connection hole pattern is 0.22 xcexcm for a stepped portion of a height of 100 nm. Besides, it is 0.25 xcexcm for a stepped portion of a height of 200 nm. Like this, as the stepped portion becomes lower, the resolution at the photolithography step becomes higher. Especially, it is important to make the height of the stepped portion 100 nm or less. Accordingly, it has been difficult to form the upper layer hard mask to be thicker than 100 nm.
Incidentally, although there is an electron beam direct drawing as an exposure method which does not receive an influence of reflection by an under stepped portion, that is, which does not use the antireflection film, since this exposure method raises costs, it is not a technique for mass production at present.
The present invention has been made to solve the above problems and provides a method of manufacturing a semiconductor device.
According to the present invention, a method of manufacturing a semiconductor device comprises a step of forming, in a laminated manner, a first insulating film in which a connection hole is formed and a second insulating film in which a wiring groove communicating with the connection hole is formed, a step of forming mask layers of plural layers on the second insulating film, and a step of forming the connection hole in the first insulating film and forming the wiring groove in the second insulating film while the mask layers of the plural layers are used; and the step of forming the mask layers of the plural layers includes a step of forming a first mask layer, in which a connection hole pattern is formed, of a same material as the first insulating film on the second insulating film, a step of forming a wiring groove pattern in a second mask layer after the second mask layer is formed on the first mask layer, a step of forming a third mask layer of a same material as the first mask layer on the second mask layer including an inner portion of the wiring groove pattern, and a step of forming the connection hole pattern extending through the third mask layer and the first mask layer.
Since the method of manufacturing the semiconductor device comprises the step of forming the third mask layer on the second mask layer including the inner portion of the wiring groove pattern, when the connection hole is formed in the first insulating film by carrying out etching of a silicon oxide film, the third mask layer is etched at the initial stage of the etching, and there occurs such a state that the second mask layer is protected by the third mask layer. When the third mask layer is removed by etching of the silicon oxide film and the second mask layer is exposed, thereafter, the second mask layer becomes an etching mask and the wiring groove pattern is formed to extend into the first mask layer, and further, the second insulating film becomes an etching mask and the connection hole is formed to pass through the first insulating film.
Like this, in the etching for formation of the connection hole, since the third mask layer has been formed, the whole load of the etching for the formation of the connection hole and the formation of the wiring groove pattern is not applied to the second mask layer. That is, at the initial stage of the etching, the etching is applied to the third mask layer, and after the third mask layer is removed by the etching, the second mask layer becomes the etching mask, so that even if over etching is carried out, the second mask layer is not excessively etched.
Further, since the third mask layer is formed of the same material as the first mask layer, as the first mask layer is etched, the third mask layer is also etched, and is removed when the connection hole is formed in the first insulating film. Thus, it is not necessary to provide a step of removing the third mask layer.
Besides, since the third mask layer is formed, it is not necessary to form the second mask layer to be thick, so that the thickness of the second mask layer can be made 100 nm or less. Therefore, a stepped portion on the surface of the third mask layer formed on the second mask layer also can be made 100 nm or less. Thus, lowering of the resolution by the stepped portion at the lithography step of forming the connection hole pattern is suppressed.
Besides, since the method of the invention comprises the step of forming the first mask layer, in which the connection hole pattern is formed, of the same material as the first insulating film on the second insulating film, when the second insulating film is etched while the first mask layer is used as the etching mask, the first insulating film functions as an etching stopper.